Dynamic QoS management for chip multiprocessors

Resource Management in Single-chip Multiprocessors

Wire Management for Coherence Traffic in Chip Multiprocessors

Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future billion transistor architectures due to their low design complexity, high clock frequency, and high throughput. In a typical CMP architecture, the L2 cache is shared by multiple cores and data coherence is maintained ...

Hardware-oriented Cache Management for Large-scale Chip Multiprocessors

One of the key requirements to obtaining high performance from chip multiprocessors (CMPs) is to effectively manage the limited on-chip cache resources shared among co-scheduled threads/processes. This thesis proposes new hardware-oriented solutions for distributed CMP caches. Computer architects are faced with growing challenges when designing cache systems for CMPs. These challenges result fr...

1 OpenMP for Chip Multiprocessors

Modern System-on-Chip (SOC) design shows a clear trend towards integration of multiple processor cores, the SOC System Section of the "International Technology Roadmap for Semiconductors" (http://public.itrs.net/) predicts that the number of processor cores will increase dramatically to match the processing demands of future applications. Providers like Intel, IBM, TI, Motorola, and Cradle have...

Processor allocator for chip multiprocessors